1. Technical Field
The present invention generally relates to semiconductor devices and methods of fabricating semiconductor devices. More particularly, the invention relates to inducing physical stress on a channel region of a FinFET device.
2. Background Information
The overall performance of integrated circuits (ICs) and semiconductor devices relies on the performance of transistors, such as FinFETs. An increase of current flow through a channel region situated under a gate dielectric and between the source and drain region, leads to an increase in the charge carrier mobility in the channel region. An increase in the charge carrier mobility in a transistor channel leads to a enhanced channel conductivity during operation and correspondingly faster device operation. One way to influence charge carrier mobility in a channel is to create tensile or compressive stress in the channel region to produce a corresponding strain in the channel region which, in turn, results in a modified mobility for electrons and holes respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, thereby enhancing the performance of N-type transistors. On the other hand, creating compressive strain in the channel region may increase the mobility of holes, thereby enhancing the performance of P-type transistors.
Current techniques involve creating tensile or compressive stress that may result in corresponding strain, in or below the channel region by introducing stress-inducing materials such as silicon/germanium layer or silicon/carbon layer or tungsten layer. Although the transistor performance may be considerably enhanced by the introduction of stress-inducing materials, continued significant efforts have to be made in increasing the stress in the channel region.
Hence, there continues to be a need to fabricate semiconductor devices with increased charge carrier mobility.